Interactive computer systems include a display device, such as a Cathode Ray Tube (CRT) or a liquid crystal display which enables the system to display information generated by the computer. Often, the display device is a raster scanned device. A typical display mechanism of a computer is shown in FIG. 1. Memory 10 contains the information about the individual pixels that are displayed on the display monitor 22. This information is provided to the memory 10 by the host computer over bus 9. Video controller 12 determines what information needs to be accessed from memory 10, which is often Video RAM (VRAM), then accesses the memory to obtain the information. The information is passed on to RAMDAC 14 which converts the digital information to an analog signal carried by the signal lines 16, 18, and 20. The signal lines are connected to the red, green, blue input of the display monitor 22. Once the display monitor 22 receives the signals, it generates on the screen the image that is represented by the information on the signal lines.
An important part of the display circuit is the video controller 12. Its most important task is to constantly refresh the display. In this process, the video controller 12 has to generate control signals for controlling various components, access the memory and fetch the information, possibly transform the information or interpret the information, and transfer the information to the RAMDAC 14. All of these tasks are done by different modules that form the video controller 12. Among the modules within the video controller 12 are Video Timing Generator (for generating video timing information for the display device) and Display ID generator (for generating display mode information).
FIG. 2 shows a typical prior art implementation of a video timing generator. This implementation may be found in prior art computer systems including the Personal Iris computer from Silicon Graphics of Mountain View, Calif. Memory 20 is coupled to the Address Counter 25 which generates the address of the information desired by the video timing generator circuit. Memory 20 may be part of memory 10 or may be separate memory. The Address Counter 25 addresses memory 20 via address bus 27. The information contained in the addressed memory location is transferred to the State Register 22 and Run Counter 23 via Data Bus 28. The State Machine 21 looks at the information out of memory 20 and determines whether the information should be loaded in State Register 22 and Run Counter 23, or it should be interpreted to determine the next step in the process.
It will be appreciated that memory 20 contains two tables, line table and frame table, which hold the video timing information. An example of the line table and frame table can be seen in FIGS. 3a and 3b respectively. The frame table contains a starting address to each line in the particular frame. The line table contains information representing the state and duration of the state for each line in a frame. A plurality of state and duration combination represent one line and is terminated by a state and duration information that is decoded by the state machine 21 to signal the end of a particular line ("EOL"). Each state represents a plurality of timing signals (e.g. composite Synch) which exist on the line for a group of consecutive pixels and the number of pixels in the group are represented by the duration of the state. A single pixel could be a group, although this is rare.
The function of the Video Timing Generator can be better understood using the flowchart of FIG. 4. The first step is to load the address of the first line in the frame table into the line counter (box 42). This will enable the system to address the memory location in the line table and get the first state and duration information in the first line (box 44). The state and duration information is then respectively loaded in state register 22 and run counter 23 of FIG. 2. The state information represents the state, high or low state, of timing signals for a group of pixels and the duration information tells the system the number of times (pixels) each state holds. Once the duration information is loaded in the run counter, it starts to count down to zero. Once run counter has reached zero (box 47), it will generate a signal which enables the state register and run counter to be loaded with the next state and duration information in the particular line. The system will continue until state machine 21 in FIG. 2 detects the end of the line (EOL) information (box 46). To detect the EOL information, state machine 21 (FIG. 2) looks for a predetermined set of bits and if any state and duration combination matches that predetermined set of bits, the state machine generates a signal to load in the address of the next line listed in the frame table (box 48).
After the new address is loaded, the state machine 21 (FIG. 2) checks the new address to see whether the end of the frame has been reached (box 49). If the end of the frame is reached (i.e. the answer to the question in box 49 is yes), the address of the first line in the frame will be loaded into line counter. If the end of the frame table is not detected (i.e. the answer to the question in box 49 is no), state machine 21 (FIG. 2) loads the state and duration information of the new line into the state register 22 and run counter 23 (FIG. 2). This process continues until the system is aborted.
In order for the memory in the prior art to work with any pixel clock rate, it has to be able to handle the frequency of such pixel clock rate. This requirement limits the performance of prior art devices where the clock rate is so high that readily available memory cannot service that rate and consequently, more expensive, exotic high speed memory is required. Furthermore, such high speed memory eliminates any possibility of allowing other modules in the video controller to use the memory capacity. Thus, memory for the video timing cannot be shared with other uses, such as display ID information.
Regarding the Display ID generator, the prior art uses the same architecture discussed above for the video timing generator, such as the architecture shown in FIG. 2. Hence, all the disadvantages mentioned above apply to a typical prior art Display ID generator.
The present invention discloses an apparatus and a method to generate video timing information and Display ID information where the memory does not have to be as fast as the pixel clock rate is. Further, by eliminating high speed compatibility requirements for the memory, it can be shared among all the modules forming the video controller circuit.